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move register-related code to separate files, move DWARF module & handle

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to pst_context, move get_frame() from pst_handler to pst_function
This commit is contained in:
nnosov
2020-01-28 14:24:32 +04:00
parent f9635841f6
commit c2fdeccd34
9 changed files with 271 additions and 180 deletions
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framework/dwarf_operations.cpp
-88
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@@ -11,82 +11,6 @@
#include "dwarf_operations.h"
#include "common.h"
dwarf_reg_map reg_map[] = {
// GP Registers
{0x0, "RAX", DW_OP_reg0},
{0x1, "RDX", DW_OP_reg1},
{0x2, "RCX", DW_OP_reg2},
{0x3, "RBX", DW_OP_reg3},
{0x4, "RSI", DW_OP_reg4},
{0x5, "RDI", DW_OP_reg5},
{0x6, "RBP", DW_OP_reg6},
{0x7, "RSP", DW_OP_reg7},
// Extended GP Registers
{0x8, "R8", DW_OP_reg8},
{0x9, "R9", DW_OP_reg9},
{0xA, "R10", DW_OP_reg10},
{0xB, "R11", DW_OP_reg11},
{0xC, "R12", DW_OP_reg12},
{0xD, "R13", DW_OP_reg13},
{0xE, "R14", DW_OP_reg14},
{0xF, "R15", DW_OP_reg15},
{0x10, "RIP", DW_OP_reg16}, // Return Address (RA) mapped to RIP
// SSE Vector Registers
{0x11, "XMM0", DW_OP_reg17},
{0x12, "XMM1", DW_OP_reg18},
{0x13, "XMM2", DW_OP_reg19},
{0x14, "XMM3", DW_OP_reg20},
{0x15, "XMM4", DW_OP_reg21},
{0x16, "XMM5", DW_OP_reg22},
{0x17, "XMM6", DW_OP_reg23},
{0x18, "XMM7", DW_OP_reg24},
{0x19, "XMM8", DW_OP_reg25},
{0x1a, "XMM9", DW_OP_reg26},
{0x1b, "XMM10", DW_OP_reg27},
{0x1c, "XMM11", DW_OP_reg28},
{0x1d, "XMM12", DW_OP_reg29},
{0x1e, "XMM13", DW_OP_reg30},
{0x1f, "XMM14", DW_OP_reg31},
// GP Registers
{0x0, "RAX", DW_OP_breg0},
{0x1, "RDX", DW_OP_breg1},
{0x2, "RCX", DW_OP_breg2},
{0x3, "RBX", DW_OP_breg3},
{0x4, "RSI", DW_OP_breg4},
{0x5, "RDI", DW_OP_breg5},
{0x6, "RBP", DW_OP_breg6},
{0x7, "RSP", DW_OP_breg7},
// Extended GP Registers
{0x8, "R8", DW_OP_breg8},
{0x9, "R9", DW_OP_breg9},
{0xA, "R10", DW_OP_breg10},
{0xB, "R11", DW_OP_breg11},
{0xC, "R12", DW_OP_breg12},
{0xD, "R13", DW_OP_breg13},
{0xE, "R14", DW_OP_breg14},
{0xF, "R15", DW_OP_breg15},
{0x10, "RIP", DW_OP_breg16}, // Return Address (RA) mapped to RIP
// SSE Vector Registers
{0x11, "XMM0", DW_OP_breg17},
{0x12, "XMM1", DW_OP_breg18},
{0x13, "XMM2", DW_OP_breg19},
{0x14, "XMM3", DW_OP_breg20},
{0x15, "XMM4", DW_OP_breg21},
{0x16, "XMM5", DW_OP_breg22},
{0x17, "XMM6", DW_OP_breg23},
{0x18, "XMM7", DW_OP_breg24},
{0x19, "XMM8", DW_OP_breg25},
{0x1a, "XMM9", DW_OP_breg26},
{0x1b, "XMM10", DW_OP_breg27},
{0x1c, "XMM11", DW_OP_breg28},
{0x1d, "XMM12", DW_OP_breg29},
{0x1e, "XMM13", DW_OP_breg30},
{0x1f, "XMM14", DW_OP_breg31},
};
int regnum = sizeof(reg_map) / sizeof(dwarf_reg_map);
// not implemented operations
bool dw_op_notimpl(dwarf_stack* stack, const dwarf_op_map* map, Dwarf_Word op1, Dwarf_Word op2)
{
@@ -1055,18 +979,6 @@ dwarf_op_map op_map[] = {
{DW_OP_GNU_entry_value, "DW_OP_GNU_entry_value", dw_op_notimpl}, // seems that it's equal to DW_OP_entry_value from DWARF 5
};
int find_regnum(uint32_t op)
{
for(uint32_t i = 0; i < sizeof(reg_map) / sizeof(dwarf_reg_map); ++i) {
if(reg_map[i].op_num == op) {
return reg_map[i].regno;
return true;
}
}
return -1;
}
const dwarf_op_map* find_op_map(int op)
{
for(uint32_t i = 0; i < sizeof(op_map) / sizeof(dwarf_op_map); ++i) {