move register-related code to separate files, move DWARF module & handle
to pst_context, move get_frame() from pst_handler to pst_function
This commit is contained in:
@@ -0,0 +1,152 @@
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/*
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* registers.cpp
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*
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* Created on: Jan 27, 2020
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* Author: nnosov
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*/
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#include <dwarf.h>
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#include <elfutils/libdwfl.h>
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#include "common.h"
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#include "registers.h"
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#include "dwarf_operations.h"
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dwarf_reg_map reg_map[] = {
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// GP Registers
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{0x0, "RAX", DW_OP_reg0},
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{0x1, "RDX", DW_OP_reg1},
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{0x2, "RCX", DW_OP_reg2},
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{0x3, "RBX", DW_OP_reg3},
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{0x4, "RSI", DW_OP_reg4},
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{0x5, "RDI", DW_OP_reg5},
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{0x6, "RBP", DW_OP_reg6},
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{0x7, "RSP", DW_OP_reg7}, // Stack pointer address (SP) mapped to RSP
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// Extended GP Registers
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{0x8, "R8", DW_OP_reg8},
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{0x9, "R9", DW_OP_reg9},
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{0xA, "R10", DW_OP_reg10},
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{0xB, "R11", DW_OP_reg11},
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{0xC, "R12", DW_OP_reg12},
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{0xD, "R13", DW_OP_reg13},
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{0xE, "R14", DW_OP_reg14},
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{0xF, "R15", DW_OP_reg15},
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{0x10, "RIP", DW_OP_reg16}, // Return Address (RA) mapped to RIP
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// SSE Vector Registers
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{0x11, "XMM0", DW_OP_reg17},
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{0x12, "XMM1", DW_OP_reg18},
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{0x13, "XMM2", DW_OP_reg19},
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{0x14, "XMM3", DW_OP_reg20},
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{0x15, "XMM4", DW_OP_reg21},
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{0x16, "XMM5", DW_OP_reg22},
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{0x17, "XMM6", DW_OP_reg23},
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{0x18, "XMM7", DW_OP_reg24},
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{0x19, "XMM8", DW_OP_reg25},
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{0x1a, "XMM9", DW_OP_reg26},
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{0x1b, "XMM10", DW_OP_reg27},
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{0x1c, "XMM11", DW_OP_reg28},
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{0x1d, "XMM12", DW_OP_reg29},
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{0x1e, "XMM13", DW_OP_reg30},
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{0x1f, "XMM14", DW_OP_reg31},
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// GP Registers
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{0x0, "RAX", DW_OP_breg0},
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{0x1, "RDX", DW_OP_breg1},
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{0x2, "RCX", DW_OP_breg2},
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{0x3, "RBX", DW_OP_breg3},
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{0x4, "RSI", DW_OP_breg4},
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{0x5, "RDI", DW_OP_breg5},
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{0x6, "RBP", DW_OP_breg6},
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{0x7, "RSP", DW_OP_breg7},
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// Extended GP Registers
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{0x8, "R8", DW_OP_breg8},
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{0x9, "R9", DW_OP_breg9},
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{0xA, "R10", DW_OP_breg10},
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{0xB, "R11", DW_OP_breg11},
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{0xC, "R12", DW_OP_breg12},
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{0xD, "R13", DW_OP_breg13},
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{0xE, "R14", DW_OP_breg14},
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{0xF, "R15", DW_OP_breg15},
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{0x10, "RIP", DW_OP_breg16}, // Return Address (RA) mapped to RIP
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// SSE Vector Registers
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{0x11, "XMM0", DW_OP_breg17},
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{0x12, "XMM1", DW_OP_breg18},
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{0x13, "XMM2", DW_OP_breg19},
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{0x14, "XMM3", DW_OP_breg20},
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{0x15, "XMM4", DW_OP_breg21},
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{0x16, "XMM5", DW_OP_breg22},
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{0x17, "XMM6", DW_OP_breg23},
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{0x18, "XMM7", DW_OP_breg24},
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{0x19, "XMM8", DW_OP_breg25},
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{0x1a, "XMM9", DW_OP_breg26},
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{0x1b, "XMM10", DW_OP_breg27},
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{0x1c, "XMM11", DW_OP_breg28},
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{0x1d, "XMM12", DW_OP_breg29},
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{0x1e, "XMM13", DW_OP_breg30},
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{0x1f, "XMM14", DW_OP_breg31},
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};
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int regnum = sizeof(reg_map) / sizeof(dwarf_reg_map);
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int find_regnum(uint32_t op)
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{
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for(int i = 0; i < regnum; ++i) {
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if(reg_map[i].op_num == op) {
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return reg_map[i].regno;
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}
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}
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return -1;
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}
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pst_reg_error pst_get_reg(pst_context* ctx, int regno, uint64_t& regval)
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{
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#ifdef USE_LIBUNWIND
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int ret = unw_get_reg(ctx->curr_frame, regno, ®val);
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switch (ret) {
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case UNW_EUNSPEC:
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return REG_CFI_ERROR;
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break;
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case UNW_EBADREG:
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return REG_UNDEFINED;
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break;
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default:
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return REG_UNDEFINED;
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break;
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}
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return REG_OK;
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#else
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Dwarf_Op ops_mem[3];
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Dwarf_Op* ops;
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size_t nops;
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char str[512];
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if(dwarf_frame_register(ctx->frame, regno, ops_mem, &ops, &nops) != -1) {
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if(nops != 0 || ops != ops_mem) {
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if(nops != 0 || ops != NULL) {
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str[0] = 0;
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ctx->print_expr_block(ops, nops, str, sizeof(str));
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dwarf_stack st(ctx);
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if(st.calc_expression(ops, nops, NULL) && st.get_value(regval)) {
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ctx->log(SEVERITY_DEBUG, "CFI register 0x%X(%s) expression: %s ==> %#lX", regno, reg_map[regno].regname, str, regval);
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return REG_OK;
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} else {
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ctx->log(SEVERITY_ERROR, "Failed to calculate register 0x%X(%s) CFI expression %s", regno, reg_map[regno].regname, str);
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return REG_EXPR_ERROR;
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}
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} else {
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ctx->log(SEVERITY_DEBUG, "CFI expression for register 0x%X(%s) is SAME VALUE", regno, reg_map[regno].regname);
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return REG_SAME;
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}
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} else {
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ctx->log(SEVERITY_DEBUG, "CFI expression for register 0x%X(%s) is UNDEFINED", regno, reg_map[regno].regname);
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return REG_UNDEFINED;
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}
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} else {
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ctx->log(SEVERITY_ERROR, "Failed to get CFI expression for register 0x%X", regno);
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}
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return REG_CFI_ERROR;
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#endif
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}
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